Because energy consumption of a circuit is quadradically dependent on the supply voltage (E∝CVdd2, where Vdd is the supply voltage) to the circuit, moderate reductions in supply voltage can provide significant power savings. As a result, complex integrated circuits, for example, microprocessors, are designed using lower and lower supply voltages. However, one disadvantage of lower supply voltages is generally increased delay times
  (            D      ∝                        V          dd                                      (                                          V                dd                            -                              V                T                                      )                    α                      ,  where VT is the threshold voltage and α is strongly dependent on the mobility degradation of elections in transistors).
One prior solution is to use higher supply voltages for circuits on a critical path of a processor and a lower voltage for circuits not on the critical path of the processor. Because the circuits not on the critical path of the processor can operate with increased delay times and not detrimentally effect the overall operation of processor, this solution can provide power savings. Further analysis of this solution is provided by D. Marculescu, “Power Efficient Processors Using Multiple Supply Voltages”, Workshop on Compilers and Operating Systems for Low Power, 2000 and M. C. Johnson, et al., “Datapath Scheduling with Multiple Supply Voltages and Level Converters”, Proceedings of the IEEE International Symposium on Circuits and Systems, 1997 (Hong Kong). However, these solutions provide lower supply voltages (and therefore power savings) only to a portion of the processor.